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authorDuncan Laurie <dlaurie@chromium.org>2016-05-16 12:53:12 -0700
committerDuncan Laurie <dlaurie@google.com>2016-05-21 06:00:38 +0200
commit2f6fb9f5f9b972fc1f19cc743e9d75ede15e5f02 (patch)
tree632fb990f052ad5215318bc5f5e64cfc2fae00f6 /src/soc/intel/skylake
parentd9af3cecaedeb3579bc7afcde586477827095f73 (diff)
downloadcoreboot-2f6fb9f5f9b972fc1f19cc743e9d75ede15e5f02.tar.xz
skylake: Add ACPI device name handler
Add a global ACPI device name handler for the Skylake SOC that will translate skylake device paths into an ACPI path that matches the device objects delcared in the DSDT at soc/intel/skylake/acpi/*. The skylake implementation uses a global acpi_name handler for the SOC and it is not necessary to add a function to every device. This function is used by device drivers calling acpi_device_name() and acpi_device_path() to generate ACPI AML in the SSDT. Change-Id: I31cecf7905a51224e7bfc40c6c4ad2487f039097 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14841 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.c69
-rw-r--r--src/soc/intel/skylake/include/soc/ramstage.h1
2 files changed, 70 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dbf7785888..f990d2b4a6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/util.h>
+#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
#include <soc/pci_devs.h>
@@ -221,6 +222,69 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
};
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+const char *soc_acpi_name(struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ switch (dev->path.pci.devfn) {
+ case SA_DEVFN_ROOT: return "MCHC";
+ case SA_DEVFN_IGD: return "GFX0";
+ case PCH_DEVFN_ISH: return "ISHB";
+ case PCH_DEVFN_XHCI: return "XHCI";
+ case PCH_DEVFN_USBOTG: return "XDCI";
+ case PCH_DEVFN_THERMAL: return "THRM";
+ case PCH_DEVFN_CIO: return "ICIO";
+ case PCH_DEVFN_I2C0: return "I2C0";
+ case PCH_DEVFN_I2C1: return "I2C1";
+ case PCH_DEVFN_I2C2: return "I2C2";
+ case PCH_DEVFN_I2C3: return "I2C3";
+ case PCH_DEVFN_ME: return "MEI1";
+ case PCH_DEVFN_ME_2: return "MEI2";
+ case PCH_DEVFN_ME_IDER: return "MEID";
+ case PCH_DEVFN_ME_KT: return "MEKT";
+ case PCH_DEVFN_ME_3: return "MEI3";
+ case PCH_DEVFN_SATA: return "SATA";
+ case PCH_DEVFN_UART2: return "UAR2";
+ case PCH_DEVFN_I2C4: return "I2C4";
+ case PCH_DEVFN_I2C5: return "I2C5";
+ case PCH_DEVFN_PCIE1: return "RP01";
+ case PCH_DEVFN_PCIE2: return "RP02";
+ case PCH_DEVFN_PCIE3: return "RP03";
+ case PCH_DEVFN_PCIE4: return "RP04";
+ case PCH_DEVFN_PCIE5: return "RP05";
+ case PCH_DEVFN_PCIE6: return "RP06";
+ case PCH_DEVFN_PCIE7: return "RP07";
+ case PCH_DEVFN_PCIE8: return "RP08";
+ case PCH_DEVFN_PCIE9: return "RP09";
+ case PCH_DEVFN_PCIE10: return "RP10";
+ case PCH_DEVFN_PCIE11: return "RP11";
+ case PCH_DEVFN_PCIE12: return "RP12";
+ case PCH_DEVFN_UART0: return "UAR0";
+ case PCH_DEVFN_UART1: return "UAR1";
+ case PCH_DEVFN_GSPI0: return "SPI0";
+ case PCH_DEVFN_GSPI1: return "SPI1";
+ case PCH_DEVFN_EMMC: return "EMMC";
+ case PCH_DEVFN_SDIO: return "SDIO";
+ case PCH_DEVFN_SDCARD: return "SDXC";
+ case PCH_DEVFN_LPC: return "LPCB";
+ case PCH_DEVFN_P2SB: return "P2SB";
+ case PCH_DEVFN_PMC: return "PMC_";
+ case PCH_DEVFN_HDA: return "HDAS";
+ case PCH_DEVFN_SMBUS: return "SBUS";
+ case PCH_DEVFN_SPI: return "FSPI";
+ case PCH_DEVFN_GBE: return "IGBE";
+ case PCH_DEVFN_TRACEHUB:return "THUB";
+ }
+
+ return NULL;
+}
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
@@ -231,11 +295,16 @@ static struct device_operations pci_domain_ops = {
.set_resources = &pci_domain_set_resources,
.scan_bus = &pci_domain_scan_bus,
.ops_pci_bus = &pci_bus_default_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_name = &soc_acpi_name,
+#endif
};
static struct device_operations cpu_bus_ops = {
.init = &soc_init_cpus,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = generate_cpu_entries,
+#endif
};
static void soc_enable(device_t dev)
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
index 2cd2d16050..55f9972e4a 100644
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -24,6 +24,7 @@
void pch_enable_dev(device_t dev);
void soc_init_pre_device(void *chip_info);
void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
extern struct pci_operations soc_pci_ops;