summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2015-07-23 20:48:06 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-07-29 19:30:49 +0200
commit8dfa660a68be3e5268c78f2a6e6643795beed76f (patch)
treec47dd37e2aae4c2f00ec0a79a6c9184bfcff7b27 /src/soc/intel/skylake
parent4f5efb6c21a9e909384a970bad410d11bdbda7a5 (diff)
downloadcoreboot-8dfa660a68be3e5268c78f2a6e6643795beed76f.tar.xz
skylake: provide pcr helper to get a port's register space
In order to aid users of the PCR register space provide pcr_port_regs(). BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0 Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288193 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/include/soc/pcr.h5
-rw-r--r--src/soc/intel/skylake/pcr.c5
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h
index 3f8ee2f281..c8a4425fcc 100644
--- a/src/soc/intel/skylake/include/soc/pcr.h
+++ b/src/soc/intel/skylake/include/soc/pcr.h
@@ -85,6 +85,8 @@
#define PID_DMI 0xEF
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+#include <stdint.h>
+
/* All these return 0 on success and < 0 on errror. */
int pcr_read32(u8 pid, u16 offset, u32 *outdata);
int pcr_read16(u8 pid, u16 offset, u16 *outdata);
@@ -95,6 +97,9 @@ int pcr_write8(u8 pid, u16 offset, u8 indata);
int pcr_andthenor32(u8 pid, u16 offset, u32 anddata, u32 ordata);
int pcr_andthenor16(u8 pid, u16 offset, u16 anddata, u16 ordata);
int pcr_andthenor8(u8 pid, u16 offset, u8 anddata, u8 ordata);
+
+/* Get the starting address of the port's registers. */
+uint8_t *pcr_port_regs(u8 pid);
#endif /* if !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _SOC_PCR_H_ */
diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c
index 0e97265497..7efbb2547a 100644
--- a/src/soc/intel/skylake/pcr.c
+++ b/src/soc/intel/skylake/pcr.c
@@ -34,6 +34,11 @@ static inline void *pcr_reg_address(u8 pid, u16 offset)
return (void *)reg_addr;
}
+uint8_t *pcr_port_regs(u8 pid)
+{
+ return pcr_reg_address(pid, 0);
+}
+
/*
* Read PCR register. (This is internal function)
* It returns PCR register and size in 1/2/4 bytes.