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authorDuncan Laurie <dlaurie@chromium.org>2018-03-26 02:24:18 -0700
committerDuncan Laurie <dlaurie@chromium.org>2018-03-28 22:52:38 +0000
commitf5116952bb77ac361ad541dea00d9df28067219e (patch)
tree16ef5146141c8cd340d6f67605234870f36c89d6 /src/soc/intel/skylake
parent8b76605a4af9b45894c39cd7b9c480bd96f523cd (diff)
downloadcoreboot-f5116952bb77ac361ad541dea00d9df28067219e.tar.xz
soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/chip.c10
-rw-r--r--src/soc/intel/skylake/chip.h1
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c8
4 files changed, 16 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 832d7e242a..2322a5f2c7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -85,6 +85,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_VMX
+ select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_GFX_OPREGION
select SOC_INTEL_COMMON_NHLT
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index f60c08d97c..0c1dfa65e5 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/util.h>
+#include <intelblocks/xdci.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -78,7 +79,7 @@ struct chip_operations soc_intel_skylake_ops = {
/* UPD parameters to be initialized before SiliconInit */
void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
int i;
@@ -140,7 +141,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->EnableAzalia = config->EnableAzalia;
params->IoBufferOwnership = config->IoBufferOwnership;
params->DspEnable = config->DspEnable;
- params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->EnableSata = config->EnableSata;
params->SataMode = config->SataMode;
@@ -196,6 +196,12 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
params->SendVrMbxCmd = config->SendVrMbxCmd;
/* Acoustic Noise Mitigation */
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b77f6dc771..dc7986948f 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -237,7 +237,6 @@ struct soc_intel_skylake_config {
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
- u8 XdciEnable;
u8 SsicPortEnable;
/* SMBus */
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 3bc66b2501..b4fed26d1d 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
@@ -221,7 +222,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchHdaEnable = config->EnableAzalia;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
params->PchHdaDspEnable = config->DspEnable;
- params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
@@ -284,6 +284,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
/*
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