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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2016-11-18 14:36:34 -0800
committerMartin Roth <martinroth@google.com>2016-12-13 18:00:43 +0100
commitffc934d9440b5a8dabcedb4da0fa88d9a1e65e18 (patch)
tree2fd448d09b9a9c87ffbc6700f8ea25112f024e73 /src/soc/intel/skylake
parentfa97cefbb3fad90573459e57845b658c9d3351a2 (diff)
downloadcoreboot-ffc934d9440b5a8dabcedb4da0fa88d9a1e65e18.tar.xz
intel MMA: Enable MMA with FSP2.0
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/romstage.h1
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c19
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c18
3 files changed, 37 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index 08753f1ee9..41658e1dbd 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -25,7 +25,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read_wpsr(u8 *sr);
-
/* Board type */
enum board_type {
BOARD_TYPE_MOBILE = 0,
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 97c6a4526e..fb261c3c8b 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -21,6 +21,7 @@
#include <arch/cbfs.h>
#include <arch/stages.h>
#include <arch/early_variables.h>
+#include <assert.h>
#include <cbmem.h>
#include <chip.h>
#include <console/console.h>
@@ -97,6 +98,24 @@ void soc_memory_init_params(struct romstage_params *params,
}
}
+void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
+ struct mma_config_param *mma_cfg)
+{
+ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */
+ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+
+ memory_cfg->MmaTestContentPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+ memory_cfg->MmaTestContentSize =
+ region_device_sz(&mma_cfg->test_content);
+ memory_cfg->MmaTestConfigPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+ memory_cfg->MmaTestConfigSize =
+ region_device_sz(&mma_cfg->test_param);
+ memory_cfg->MrcFastBoot = 0x00;
+ memory_cfg->SaGv = 0x02;
+}
+
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
MEMORY_INIT_UPD *new)
{
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 73d726c183..e478890930 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -165,6 +165,24 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mainboard_memory_init_params(mupd);
}
+void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
+ struct mma_config_param *mma_cfg)
+{
+ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */
+ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
+
+ memory_cfg->MmaTestContentPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_content);
+ memory_cfg->MmaTestContentSize =
+ region_device_sz(&mma_cfg->test_content);
+ memory_cfg->MmaTestConfigPtr =
+ (uintptr_t) rdev_mmap_full(&mma_cfg->test_param);
+ memory_cfg->MmaTestConfigSize =
+ region_device_sz(&mma_cfg->test_param);
+ memory_cfg->MrcFastBoot = 0x00;
+ memory_cfg->SaGv = 0x02;
+}
+
__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd)
{
/* Do nothing */