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authorMatt Delco <delco@chromium.org>2020-03-09 12:41:09 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-10 20:29:10 +0000
commit54e9894353ec2c6e635bead94a94953db069d49d (patch)
tree87e67368ca7c32b89135fce97f7e99a8d3abb1db /src/soc/intel/skylake
parent49fb39b7830c849d835f0632ab2967def8fa26a9 (diff)
downloadcoreboot-54e9894353ec2c6e635bead94a94953db069d49d.tar.xz
soc/intel: fix eist enabling
There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco <delco@chromium.org> Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/cpu.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index f5273f6fc7..d7da56eaf7 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -291,14 +291,11 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
-
- if (conf->eist_enable)
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
- else
- msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
-
wrmsr(IA32_MISC_ENABLE, msr);
+ /* Set EIST status */
+ cpu_set_eist(conf->eist_enable);
+
/* Disable Thermal interrupts */
msr.lo = 0;
msr.hi = 0;