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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-24 13:43:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-04 15:43:30 +0000
commit79ccc6933284ca02d17d9e1eda9a531ce43e1f65 (patch)
tree49fe1b78916338575b1a6bec931e2fb885cc311a /src/soc/intel/skylake
parentf3161df2eba8d61445372a9c732c61a1947064bd (diff)
downloadcoreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.xz
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/acpi/globalnvs.asl2
-rw-r--r--src/soc/intel/skylake/chip.h2
-rw-r--r--src/soc/intel/skylake/include/soc/nvs.h2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index e17b2604cf..8aeb5a37f0 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -106,7 +106,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b189a16a05..2c3d3a59c8 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -226,7 +226,7 @@ struct soc_intel_skylake_config {
u8 PchDciEn;
/*
- * Pcie Root Port configuration:
+ * PCIe Root Port configuration:
* each element of array corresponds to
* respective PCIe root port.
*/
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index d5f62f63fc..24e4cf1a2a 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -88,7 +88,7 @@ typedef struct global_nvs_t {
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */