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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-29 18:31:16 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 19:27:53 +0200
commit038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch)
tree8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/intel/skylake
parentf9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff)
downloadcoreboot-038e7247dc9705ff2d47dd90ec9a807f6feb52ba.tar.xz
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/cpu.c4
-rw-r--r--src/soc/intel/skylake/smmrelocate.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index b7353cab6b..2b75e5aeb4 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -352,7 +352,7 @@ static void cpu_core_init(device_t cpu)
/* Clear out pending MCEs */
configure_mca();
- /* Enable the local cpu apics */
+ /* Enable the local CPU apics */
enable_lapic_tpr();
setup_lapic();
@@ -487,7 +487,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
* 0x08b with the Patch revision id one less than the id in the
* microcode binary. The PRMRR support is indicated in the MSR
* MTRRCAP[12]. Check for this feature and avoid reloading the
- * same microcode during cpu initialization.
+ * same microcode during CPU initialization.
*/
msr = rdmsr(MTRR_CAP_MSR);
return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 807aaa38ac..1cc8e54e55 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -138,7 +138,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
- printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
/*
* Determine if the processor supports saving state in MSRs. If so,