diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-27 12:14:38 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-28 20:29:36 +0000 |
| commit | fb15d463d2cfaceb4b45d090525179da20ca6b26 (patch) | |
| tree | 2a57f71046c595b8fd902a26f121c028223a6cfa /src/soc/intel/skylake | |
| parent | add7666a47c454df39e86c3782bf736372b765be (diff) | |
| download | coreboot-fb15d463d2cfaceb4b45d090525179da20ca6b26.tar.xz | |
soc/intel/skylake: Make use of Intel common DSP block
TEST=Build and boot soraka/eve.
Change-Id: I8be2a90dc4e4c5eb196af57045d2a46b7f0c9722
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/dsp.c | 33 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 4 |
4 files changed, 1 insertions, 38 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e5cc4f7ad2..053239ab8e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index da45ec54a2..3a6dd2d1dd 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -46,7 +46,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c ramstage-y += cpu.c -ramstage-y += dsp.c ramstage-y += elog.c ramstage-y += finalize.c ramstage-y += gpio.c diff --git a/src/soc/intel/skylake/dsp.c b/src/soc/intel/skylake/dsp.c deleted file mode 100644 index 13051a0558..0000000000 --- a/src/soc/intel/skylake/dsp.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/ramstage.h> - -static struct device_operations dsp_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_static_bus, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver skylake_dsp __pci_driver = { - .ops = &dsp_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x9d70 -}; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 28f2f391af..4fc8807281 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -44,10 +44,6 @@ #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP _SA_DEVFN(DSP) -#define SA_DEV_DSP _SA_DEV(DSP) - /* PCH Devices */ #define PCH_DEV_SLOT_ISH 0x13 |