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authorNaresh G Solanki <naresh.solanki@intel.com>2018-10-15 15:37:15 +0530
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:44:03 +0000
commit84fbc30e928d28fba2f3a25f6ccea3a831dce648 (patch)
tree174629abb4eb412ab6bac8655715faadb993e690 /src/soc/intel/skylake
parent2653cdbe0cbe2aefbe98503ae8d34d80dc8c69c9 (diff)
downloadcoreboot-84fbc30e928d28fba2f3a25f6ccea3a831dce648.tar.xz
soc/intel/skylake: Prevent disabling of TCO
In Skylake/Kabylake, if ACPI PM timer is disabled then TCO also gets disabled & vice versa. FSP default config for EnableTcoTimer is disabled, this caused ACPI PM timer & TCO to be disabled by FSP even when config PmTimerDisable = 0. Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config PmTimerDisable. BUG=None TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused reboot after running shell command: cat >> /dev/watchdog0 Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/29108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index a2a430e695..7cc6de51f7 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -369,6 +369,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SataMode = config->SataMode;
params->SataSpeedLimit = config->SataSpeedLimit;
params->SataPwrOptEnable = config->SataPwrOptEnable;
+ params->EnableTcoTimer = !config->PmTimerDisabled;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;