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authorFelix Singer <felixsinger@posteo.net>2020-07-25 08:40:15 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-29 20:47:56 +0000
commitffe90c528b0487ce47a123ae905be8823c5615ae (patch)
tree9d011606a5318d5d1da7a014cbc92dcf85ecc6ea /src/soc/intel/skylake
parent57c8143350bf357dd7edc13ddf735084eea53d07 (diff)
downloadcoreboot-ffe90c528b0487ce47a123ae905be8823c5615ae.tar.xz
soc/intel/skylake: Enable SMBus depending on devicetree configuration
Currently SMBus gets enabled by the option SmbusEnable, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SMBus controller. I checked all corresponding mainboards if the devicetree configuration matches the SmbusEnable setting. Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.h3
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c6
2 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b243bdea75..243e6ee851 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -272,9 +272,6 @@ struct soc_intel_skylake_config {
struct usb3_port_config usb3_ports[10];
u8 SsicPortEnable;
- /* SMBus */
- u8 SmbusEnable;
-
/*
* SerialIO device mode selection:
*
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 99f444ad5e..8e789bce80 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -272,6 +272,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_skylake_config *config;
+ const struct device *dev;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
@@ -296,8 +297,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
- /* Enable SMBus controller based on config */
- m_cfg->SmbusEnable = config->SmbusEnable;
+ /* Enable SMBus controller */
+ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
+ m_cfg->SmbusEnable = dev ? dev->enabled : 0;
/* Set primary graphic device */
soc_primary_gfx_config_params(m_cfg, config);