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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-07-16 09:03:06 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-14 07:02:26 +0000 |
| commit | c1d227d3120470a9e0b0d9d6f58d334782117820 (patch) | |
| tree | 6a9ccc01bd28988187346c64184468a36bc800bf /src/soc/intel/skylake | |
| parent | 1ba86f685b87c2467518eb04beaa36f16349570f (diff) | |
| download | coreboot-c1d227d3120470a9e0b0d9d6f58d334782117820.tar.xz | |
soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.
The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.
TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.
Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.
BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
CAR configuration.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18ecd..db0f6882ae 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER - select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -79,6 +78,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select USE_CAR_NEM_ENHANCED_V1 config FSP_HYPERTHREADING bool "Enable Hyper-Threading" |