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authorWim Vervoorn <wvervoorn@eltan.com>2020-05-07 12:41:13 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-11 09:30:04 +0000
commitd6b682cf921b79752810b5df059c54659475a17c (patch)
tree0f4a6f1362c3aa5a190078daab1512894caf7ecf /src/soc/intel/skylake
parentf5472a10c6fc3f0c452c514c7a23b7046e42ac55 (diff)
downloadcoreboot-d6b682cf921b79752810b5df059c54659475a17c.tar.xz
soc/intel/skylake: Allow setting of PcieRpMaxPayload
Add setting of the MaxPayload for each root port from the device tree. By default MaxPayload is set to 128 bytes. This change allows changing to 256 bytes. BUG=N/A TEST=tested on facebook monolith Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.h6
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index b24ec4fdc0..e0baefcdda 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -188,6 +188,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
+ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+ params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index d268eebd66..d4afa1de64 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -284,6 +284,12 @@ struct soc_intel_skylake_config {
/* Enable/Disable HotPlug support for Root Port */
u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
+ /* PCIE RP Max Payload, Max Payload Size supported */
+ enum {
+ RpMaxPayload_128,
+ RpMaxPayload_256,
+ } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
+
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];