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authorSubrata Banik <subrata.banik@intel.com>2016-07-24 00:36:12 +0530
committerAndrey Petrov <andrey.petrov@intel.com>2016-07-28 05:15:58 +0200
commite4a8537ce20d801a5985ba6268ae83593063a4bf (patch)
treeefdc7dcf51a9b91f8d4f6f8db9c8a0ef951ca62d /src/soc/intel/skylake
parent68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (diff)
downloadcoreboot-e4a8537ce20d801a5985ba6268ae83593063a4bf.tar.xz
soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/Kconfig13
-rw-r--r--src/soc/intel/skylake/Makefile.inc18
-rw-r--r--src/soc/intel/skylake/bootblock/bootblock.c27
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c66
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c18
-rw-r--r--src/soc/intel/skylake/bootblock/systemagent.c4
-rw-r--r--src/soc/intel/skylake/bootblock/uart.c (renamed from src/soc/intel/skylake/romstage/uart.c)5
-rw-r--r--src/soc/intel/skylake/include/soc/bootblock.h28
-rw-r--r--src/soc/intel/skylake/include/soc/romstage.h1
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc16
-rw-r--r--src/soc/intel/skylake/romstage/pch.c3
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c18
12 files changed, 100 insertions, 117 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 5f12f5bb4a..bbffd17f6d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select ACPI_NHLT
+ select BOOTBLOCK_CONSOLE
select CACHE_MRC_SETTINGS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select C_ENVIRONMENT_BOOTBLOCK
@@ -61,22 +62,10 @@ config CHROMEOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
select VIRTUAL_DEV_SWITCH
-config BOOTBLOCK_CPU_INIT
- string
- default "soc/intel/skylake/bootblock/cpu.c"
-
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "soc/intel/skylake/bootblock/systemagent.c"
-
config BOOTBLOCK_RESETS
string
default "soc/intel/common/reset.c"
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "soc/intel/skylake/bootblock/pch.c"
-
config CBFS_SIZE
hex
default 0x200000
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 30ff7b79de..8ef8ebd09c 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -11,14 +11,18 @@ subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/cpu.c
+bootblock-y += bootblock/pch.c
+bootblock-y += bootblock/systemagent.c
+bootblock-y += bootblock/uart.c
+bootblock-y += gpio.c
+bootblock-y += monotonic_timer.c
+bootblock-y += pch.c
+bootblock-y += pcr.c
+bootblock-y += pmutil.c
+bootblock-y += tsc_freq.c
+bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
-verstage-y += gpio.c
-verstage-y += memmap.c
-verstage-y += monotonic_timer.c
-verstage-y += pch.c
-verstage-y += pmutil.c
-verstage-y += pcr.c
-verstage-y += tsc_freq.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
romstage-y += flash_controller.c
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index c7ec937566..028bb7b314 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -14,9 +14,34 @@
*/
#include <bootblock_common.h>
+#include <soc/bootblock.h>
+#include <soc/romstage.h>
void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
{
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp);
-} \ No newline at end of file
+}
+
+void bootblock_soc_early_init(void)
+{
+ bootblock_systemagent_early_init();
+ bootblock_pch_early_init();
+ bootblock_cpu_init();
+
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+ pch_uart_init();
+}
+
+/*
+ * Perform early chipset initialization before fsp memory init
+ * example: pirq->irq programming, enabling smbus, pmcbase, abase,
+ * get platform info, i2c programming
+ */
+void bootblock_soc_init(void)
+{
+ report_platform_info();
+ set_max_freq();
+ pch_early_init();
+ i2c_early_init();
+}
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index d713974358..8c1e58a65f 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -15,14 +15,11 @@
*/
#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <device/pci_def.h>
+#include <delay.h>
#include <arch/io.h>
#include <cpu/intel/microcode/microcode.c>
#include <reset.h>
+#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -33,45 +30,6 @@
/* Soft Reset Data Register Bit 6-11 = Flex Ratio */
#define FLEX_RATIO_BIT 6
-static void set_var_mtrr(
- unsigned reg, unsigned base, unsigned size, unsigned type)
-
-{
- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
- msr_t basem, maskm;
- basem.lo = base | type;
- basem.hi = 0;
- wrmsr(MTRR_PHYS_BASE(reg), basem);
- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
- wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
- msr_t msr;
-
- disable_cache();
- set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
- enable_cache();
-
- /* Enable Variable MTRRs */
- msr.hi = 0x00000000;
- msr.lo = 0x00000800;
- wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
-static void bootblock_mdelay(int ms)
-{
- u32 target = ms * 24 * 1000;
- msr_t current;
- msr_t start = rdmsr(MSR_COUNTER_24_MHZ);
-
- do {
- current = rdmsr(MSR_COUNTER_24_MHZ);
- } while ((current.lo - start.lo) < target);
-}
-
static void set_pch_cpu_strap(u8 flex_ratio)
{
uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
@@ -135,31 +93,15 @@ static void set_flex_ratio_to_tdp_nominal(void)
set_pch_cpu_strap(nominal_ratio);
/* Delay before reset to avoid potential TPM lockout */
- bootblock_mdelay(30);
+ mdelay(30);
/* Issue soft reset, will be "CPU only" due to soft reset data */
soft_reset();
}
-static void check_for_clean_reset(void)
-{
- msr_t msr;
- msr = rdmsr(MTRR_DEF_TYPE_MSR);
-
- /*
- * Use the MTRR default type MSR as a proxy for detecting INIT#.
- * Reset the system if any known bits are set in that MSR. That is
- * an indication of the CPU not being properly reset.
- */
- if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN))
- soft_reset();
-}
-
-static void bootblock_cpu_init(void)
+void bootblock_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
- check_for_clean_reset();
- enable_rom_caching();
intel_update_microcode_from_cbfs();
}
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 94ed844d3b..569611502e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,9 +15,11 @@
* GNU General Public License for more details.
*/
#include <arch/io.h>
+#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
+#include <soc/pcr.h>
#include <soc/spi.h>
/*
@@ -51,8 +54,21 @@ static void enable_spibar(void)
pci_write_config8(dev, PCI_COMMAND, pcireg);
}
-static void bootblock_southbridge_init(void)
+static void enable_p2sbbar(void)
+{
+ device_t dev = PCH_DEV_P2SB;
+
+ /* Enable PCR Base address in PCH */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, PCH_PCR_BASE_ADDRESS);
+
+ /* Enable P2SB MSE */
+ pci_write_config8(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+}
+
+void bootblock_pch_early_init(void)
{
enable_spibar();
enable_spi_prefetch();
+ enable_p2sbbar();
}
diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c
index a65be99429..608110e253 100644
--- a/src/soc/intel/skylake/bootblock/systemagent.c
+++ b/src/soc/intel/skylake/bootblock/systemagent.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,10 +16,11 @@
*/
#include <arch/io.h>
+#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
-static void bootblock_northbridge_init(void)
+void bootblock_systemagent_early_init(void)
{
uint32_t reg;
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index dc417e0d7a..ff1687c520 100644
--- a/src/soc/intel/skylake/romstage/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2016 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,9 +19,9 @@
#include <console/uart.h>
#include <device/pci_def.h>
#include <stdint.h>
+#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
-#include <soc/romstage.h>
#include <soc/serialio.h>
#include <gpio.h>
@@ -53,7 +54,7 @@ void pch_uart_init(void)
/*
* Set M and N divisor inputs and enable clock.
* Main reference frequency to UART is:
- * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
+ * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
*/
tmp = read32(base + SIO_REG_PPR_CLOCK);
tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
new file mode 100644
index 0000000000..10e1e03e22
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_
+#define _SOC_SKYLAKE_BOOTBLOCK_H_
+
+/* Bootblock pre console init programing */
+void bootblock_cpu_init(void);
+void bootblock_pch_early_init(void);
+void bootblock_systemagent_early_init(void);
+
+void pch_uart_init(void);
+/* Bootblock post console init programing */
+void pch_enable_lpc(void);
+
+#endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 56bace15a7..71887aa165 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -22,7 +22,6 @@
void i2c_early_init(void);
void systemagent_early_init(void);
void pch_early_init(void);
-void pch_uart_init(void);
void intel_early_me_status(void);
void report_platform_info(void);
void set_max_freq(void);
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 6ae81378a4..7a13084bf5 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,13 +1,10 @@
-verstage-y += cpu.c
-verstage-y += i2c.c
-verstage-y += pch.c
+bootblock-y += cpu.c
+bootblock-y += i2c.c
+bootblock-y += pch.c
+bootblock-y += report_platform.c
+bootblock-y += smbus.c
+
verstage-y += power_state.c
-verstage-y += report_platform.c
-verstage-y += romstage.c
-verstage-y += smbus.c
-verstage-y += spi.c
-verstage-y += systemagent.c
-verstage-y += uart.c
romstage-y += cpu.c
romstage-y += i2c.c
@@ -18,4 +15,3 @@ romstage-y += romstage.c
romstage-y += smbus.c
romstage-y += spi.c
romstage-y += systemagent.c
-romstage-y += uart.c
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
index 1196c5eb9d..e8c41cbe81 100644
--- a/src/soc/intel/skylake/romstage/pch.c
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -57,8 +57,7 @@ static void pch_enable_lpc(void)
pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
/* IO Decode Enable */
- lpc_en = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | GAMEH_LPC_EN |
- COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
+ lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index b16e5aa22c..56a5a92255 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -49,24 +49,6 @@ void soc_pre_ram_init(struct romstage_params *params)
soc_fill_pei_data(params->pei_data);
}
-/* SOC initialization before the console is enabled. */
-void car_soc_pre_console_init(void)
-{
- /* System Agent Early Initialization */
- systemagent_early_init();
-
- if (IS_ENABLED(CONFIG_UART_DEBUG))
- pch_uart_init();
-}
-
-void car_soc_post_console_init(void)
-{
- report_platform_info();
- set_max_freq();
- pch_early_init();
- i2c_early_init();
-}
-
int get_sw_write_protect_state(void)
{
u8 status;