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authorAaron Durbin <adurbin@chromium.org>2016-11-09 17:04:15 -0600
committerAaron Durbin <adurbin@chromium.org>2016-11-11 03:11:31 +0100
commited14a4e0df25e55cea2b72a87087aaeb3540c785 (patch)
tree5a60bd779391096d6554d9b94f384f158d7c3c00 /src/soc/intel/skylake
parentce21151a1c050476079c3ce31b8e8013f8cd3282 (diff)
downloadcoreboot-ed14a4e0df25e55cea2b72a87087aaeb3540c785.tar.xz
soc/intel/skylake: move i2c voltage config to own variable
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.h4
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 879c157772..2703224883 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -163,7 +163,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SkipMpInit = config->FspSkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
- params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
+ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
/*
* To disable Heci, the Psf needs to be left unlocked
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 207c360476..a141a34916 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -40,8 +40,6 @@ enum skylake_i2c_voltage {
};
struct skylake_i2c_config {
- /* Bus voltage level, default is 3.3V */
- enum skylake_i2c_voltage voltage;
/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
enum i2c_speed speed;
/* Bus should be enabled prior to ramstage with temporary base */
@@ -201,6 +199,8 @@ struct soc_intel_skylake_config {
u8 SerialIoDevMode[PchSerialIoIndexMax];
/* I2C */
+ /* Bus voltage level, default is 3.3V */
+ enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
struct skylake_i2c_config i2c[SKYLAKE_I2C_DEV_MAX];
/* Camera */
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 98960f995e..49569d9617 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -203,7 +203,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
- params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
+ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i];
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);