drivers/intel/gma: Move IGD OpRegion to CBMEM

It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.

TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
     intel_backlight + acpi_video synchronize, both before and
     after suspend.

Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 3 insertions, 130 deletions

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index c2584db90b..abcde9421b 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -58,48 +58,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	A4GB,	64,	// 0x54 - 0x5B Base of above 4GB MMIO Resource
 	A4GS,	64,	// 0x5C - 0x63 Length of above 4GB MMIO Resource
 
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type CMOS option
-	ITVF,	 8,	// 0xba - IGD TV format CMOS option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD Power conservation feature
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-
-	ISCI,	 8,	// 0xe8 - IGD SMI/SCI mode (0: SCI)
-	PAVP,	 8,	// 0xe9 - IGD PAVP data
-	Offset (0xeb),
-	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native PCIe support
-	PLFL,	 8,	// 0xed - platform flavor
-	BREV,	 8,	// 0xee - board revision
-	DPBM,	 8,	// 0xef - digital port b mode
-	DPCM,	 8,	// 0xf0 - digital port c mode
-	DPDM,	 8,	// 0xf1 - digital port d mode
-	ALFP,	 8,	// 0xf2 - active lfp
-	IMON,	 8,	// 0xf3 - current graphics turbo imon value
-	MMIO,	 8,	// 0xf4 - 64bit mmio support
-
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 0f6e35a173..dab7e145d1 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmode.h>
-#include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <device/pci.h>
@@ -12,7 +11,6 @@
 #include <drivers/intel/gma/libgfxinit.h>
 #include <intelblocks/graphics.h>
 #include <drivers/intel/gma/opregion.h>
-#include <soc/nvs.h>
 #include <soc/ramstage.h>
 #include <types.h>
 
@@ -85,6 +83,8 @@ void graphics_soc_init(struct device *dev)
 {
 	u32 ddi_buf_ctl;
 
+	intel_gma_init_igd_opregion();
+
 	graphics_setup_panel(dev);
 
 	/*
@@ -123,56 +123,6 @@ void graphics_soc_init(struct device *dev)
 		/* Initialize PCI device, load/execute BIOS Option ROM */
 		pci_dev_init(dev);
 	}
-
-	intel_gma_restore_opregion();
-}
-
-uintptr_t gma_get_gnvs_aslb(const void *gnvs)
-{
-	const global_nvs_t *gnvs_ptr = gnvs;
-	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
-}
-
-void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
-{
-	global_nvs_t *gnvs_ptr = gnvs;
-	if (gnvs_ptr)
-		gnvs_ptr->aslb = aslb;
-}
-
-/* Initialize IGD OpRegion, called from ACPI code */
-static void update_igd_opregion(igd_opregion_t *opregion)
-{
-	/* FIXME: Add platform specific mailbox initialization */
-}
-
-uintptr_t graphics_soc_write_acpi_opregion(const struct device *device,
-		uintptr_t current, struct acpi_rsdp *rsdp)
-{
-	igd_opregion_t *opregion;
-	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
-	/* If GOP is not used, exit here */
-	if (!CONFIG(INTEL_GMA_ADD_VBT))
-		return current;
-
-	/* If IGD is disabled, exit here */
-	if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
-		return current;
-
-	printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
-	opregion = (igd_opregion_t *)current;
-
-	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
-		return current;
-	if (gnvs)
-		gnvs->aslb = (u32)(uintptr_t)opregion;
-	update_igd_opregion(opregion);
-	current += sizeof(igd_opregion_t);
-	current = acpi_align_current(current);
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-	return current;
 }
 
 const struct i915_gpu_controller_info *
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 630ceb7a78..4973597947 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -47,42 +47,7 @@ typedef struct global_nvs_t {
 	u64	elng; /* 0x4C - 0x53 EPC Length */
 	u64	a4gb; /* 0x54 - 0x5B Base of above 4GB MMIO Resource */
 	u64	a4gs; /* 0x5C - 0x63 Length of above 4GB MMIO Resource */
-	u8	rsvd[80];
-
-	/* IGD OpRegion */
-	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
-	u8	ibtt; /* 0xb8 - IGD boot type */
-	u8	ipat; /* 0xb9 - IGD panel type */
-	u8	itvf; /* 0xba - IGD TV format */
-	u8	itvm; /* 0xbb - IGD TV minor format */
-	u8	ipsc; /* 0xbc - IGD Panel Scaling */
-	u8	iblc; /* 0xbd - IGD BLC configuration */
-	u8	ibia; /* 0xbe - IGD BIA configuration */
-	u8	issc; /* 0xbf - IGD SSC configuration */
-	u8	i409; /* 0xc0 - IGD 0409 modified settings */
-	u8	i509; /* 0xc1 - IGD 0509 modified settings */
-	u8	i609; /* 0xc2 - IGD 0609 modified settings */
-	u8	i709; /* 0xc3 - IGD 0709 modified settings */
-	u8	idmm; /* 0xc4 - IGD Power Conservation */
-	u8	idms; /* 0xc5 - IGD DVMT memory size */
-	u8	if1e; /* 0xc6 - IGD Function 1 Enable */
-	u8	hvco; /* 0xc7 - IGD HPLL VCO */
-	u32	nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */
-	u8	isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */
-	u8	pavp; /* 0xe9 - IGD PAVP data */
-	u8	rsvd12; /* 0xea - rsvd */
-	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native PCIe support */
-	u8	plfl; /* 0xed - platform flavor */
-	u8	brev; /* 0xee - board revision */
-	u8	dpbm; /* 0xef - digital port b mode */
-	u8	dpcm; /* 0xf0 - digital port c mode */
-	u8	dpdm; /* 0xf1 - digital port c mode */
-	u8	alfp; /* 0xf2 - active lfp */
-	u8	imon; /* 0xf3 - current graphics turbo imon value */
-	u8	mmio; /* 0xf4 - 64bit mmio support */
-
-	u8	unused[11];
+	u8	rsvd[156];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;