diff options
| author | Duncan Laurie <dlaurie@google.com> | 2020-07-29 16:31:18 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-10-09 23:26:04 +0000 |
| commit | a5bb31f069d709f2ca9ddda4f623147df9653990 (patch) | |
| tree | 5efec6a8b9fad77214ac84d9b4c14d79f0fc3bb4 /src/soc/intel/tigerlake/Kconfig | |
| parent | e335c2e02fcf7ee15dd5ae947a19d65390729263 (diff) | |
| download | coreboot-a5bb31f069d709f2ca9ddda4f623147df9653990.tar.xz | |
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception
of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index bf05d37ad3..4df2e852ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -86,6 +86,10 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config CHIPSET_DEVICETREE + string + default "soc/intel/tigerlake/chipset.cb" + config IFD_CHIPSET string default "tgl" |