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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-29 15:20:56 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-07-07 20:31:14 +0000 |
| commit | c5316ec4d675750f35ff1b383adacc2255e92d79 (patch) | |
| tree | 9def7221ee37b1c5939f7a9d35e8ba5f0c0fd942 /src/soc/intel/tigerlake/Kconfig | |
| parent | 3452cb1359229b0457e9e1f6282c67fd459d4c90 (diff) | |
| download | coreboot-c5316ec4d675750f35ff1b383adacc2255e92d79.tar.xz | |
soc/intel/common/block: Add new block DTT
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.
Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c30519c2fa..091abb927f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA |