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| author | li feng <li1.feng@intel.com> | 2020-03-12 16:09:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-16 14:46:31 +0000 |
| commit | 2cf9d3883cc09aa2410135b87d715f47608ae38d (patch) | |
| tree | b7aff1e00851ff70f058ecdb316ceb074c2c7b88 /src/soc/intel/tigerlake/acpi/southbridge.asl | |
| parent | b159d443dd6e2bd977d30b3cb5db86b38430c1ea (diff) | |
| download | coreboot-2cf9d3883cc09aa2410135b87d715f47608ae38d.tar.xz | |
soc/intel/tigerlake: Support ISH
Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree
BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/southbridge.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 9d25a735f5..1403eb4b13 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -49,6 +49,9 @@ /* SMBus 0:1f.4 */ #include "smbus.asl" +/* ISH 0:12.0 */ +#include "ish.asl" + /* USB XHCI 0:14.0 */ #include "xhci.asl" |