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authorRavi Sarawadi <ravishankar.sarawadi@intel.com>2019-12-16 23:23:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-18 11:19:03 +0000
commit954a5b50ad9d6ee31f0f0d7abe6badf412cbe9cc (patch)
tree03e6b598cef6e8d739269ae90d21c6c7b661b5d2 /src/soc/intel/tigerlake/acpi
parent69855f2e609483b2cbe4aebf7fa6ca1dde0bfc30 (diff)
downloadcoreboot-954a5b50ad9d6ee31f0f0d7abe6badf412cbe9cc.tar.xz
soc/intel/tigerlake: Update ACPI files
Add and update ACPI files for Tiger Lake SoC Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl) Reference PCH EDS#576591 vol1 rev1.2 PCH EDS#575857 vol2 rev1.0 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/acpi')
-rw-r--r--src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl136
-rw-r--r--src/soc/intel/tigerlake/acpi/serialio.asl6
-rw-r--r--src/soc/intel/tigerlake/acpi/smbus.asl21
-rw-r--r--src/soc/intel/tigerlake/acpi/southbridge.asl10
-rw-r--r--src/soc/intel/tigerlake/acpi/xhci.asl8
5 files changed, 168 insertions, 13 deletions
diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
new file mode 100644
index 0000000000..ab1097e274
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
@@ -0,0 +1,136 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define R_ICLK_PCR_CAMERA1 0x8000
+#define B_ICLK_PCR_FREQUENCY 0x1
+#define B_ICLK_PCR_REQUEST 0x2
+
+Scope (\_SB.PCI0) {
+ /* IsCLK PCH register for clock settings */
+ OperationRegion (ICLK, SystemMemory, PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, 0x40)
+ Field (ICLK, AnyAcc, Lock, Preserve)
+ {
+ CLK1, 8,
+ Offset(0x0C),
+ CLK2, 8,
+ Offset(0x18),
+ CLK3, 8,
+ Offset(0x24),
+ CLK4, 8,
+ Offset(0x30),
+ CLK5, 8,
+ Offset(0x3C),
+ CLK6, 8,
+ }
+
+ /*
+ * Helper function for Read And OR Write
+ * Arg0 : source and destination
+ * Arg1 : And data
+ * Arg2 : Or data
+ */
+ Method (RAOW, 0x3, NotSerialized)
+ {
+ Local0 = Arg0
+ Arg0 = Local0 & Arg1 | Arg2
+ }
+
+ /*
+ * Clock Control
+ * Arg0 - Clock number (0:IMGCLKOUT_0, etc)
+ * Arg1 - Desired state (0:Disable, 1:Enable)
+ */
+ Method(CLKC, 0x2, NotSerialized)
+ {
+
+ Switch (ToInteger (Arg0))
+ {
+ Case (0)
+ {
+ RAOW (CLK1, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
+ }
+ Case (1)
+ {
+ RAOW (CLK2, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
+ }
+ Case (2)
+ {
+ RAOW (CLK3, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
+ }
+ Case (3)
+ {
+ RAOW (CLK4, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
+ }
+ Case (4)
+ {
+ RAOW (CLK5, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
+ }
+ Case (5)
+ {
+ RAOW (CLK6, ~B_ICLK_PCR_REQUEST, Arg1 << 1)
+ }
+ }
+ }
+
+ /*
+ * Clock Frequency
+ * Arg0 - Clock number (0:IMGCLKOUT_0, etc)
+ * Arg1 - Clock frequency (0:24MHz, 1:19.2MHz)
+ */
+ Method (CLKF, 0x2, NotSerialized)
+ {
+ Switch (ToInteger (Arg0))
+ {
+ Case (0)
+ {
+ RAOW (CLK1, ~B_ICLK_PCR_FREQUENCY, Arg1)
+ }
+ Case (1)
+ {
+ RAOW (CLK2, ~B_ICLK_PCR_FREQUENCY, Arg1)
+ }
+ Case (2)
+ {
+ RAOW (CLK3, ~B_ICLK_PCR_FREQUENCY, Arg1)
+ }
+ Case (3)
+ {
+ RAOW (CLK4, ~B_ICLK_PCR_FREQUENCY, Arg1)
+ }
+ Case (4)
+ {
+ RAOW (CLK5, ~B_ICLK_PCR_FREQUENCY, Arg1)
+ }
+ Case (5)
+ {
+ RAOW (CLK6, ~B_ICLK_PCR_FREQUENCY, Arg1)
+ }
+ }
+ }
+
+ /*
+ * Clock control Method
+ * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3,
+ * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5)
+ * Arg1: Clock Enable / Disable (0: Disable, 1: Enable)
+ * Arg2: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz)
+ */
+ Method (MCCT, 0x3, NotSerialized)
+ {
+ CLKF (Arg0, Arg2)
+ CLKC (Arg0, Arg1)
+ }
+}
diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl
index 0b0e3da678..95759c2dd0 100644
--- a/src/soc/intel/tigerlake/acpi/serialio.asl
+++ b/src/soc/intel/tigerlake/acpi/serialio.asl
@@ -69,6 +69,12 @@ Device (SPI2)
Name (_DDN, "Serial IO SPI Controller 2")
}
+Device (SPI3)
+{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "Serial IO SPI Controller 3")
+}
+
Device (UAR0)
{
Name (_ADR, 0x001e0000)
diff --git a/src/soc/intel/tigerlake/acpi/smbus.asl b/src/soc/intel/tigerlake/acpi/smbus.asl
new file mode 100644
index 0000000000..8febe9deef
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/smbus.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel SMBus Controller 0:1f.4 */
+
+Device (SBUS)
+{
+ Name (_ADR, 0x001f0004)
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 7de8ac42d3..8593d07326 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -25,8 +25,8 @@
/* PCR access */
#include <soc/intel/common/acpi/pcr.asl>
-/* eMMC, SD Card */
-#include "scs.asl"
+/* PCH clock */
+#include "camera_clock_ctl.asl"
/* GPIO controller */
#include "gpio.asl"
@@ -43,11 +43,11 @@
/* Serial IO */
#include "serialio.asl"
+/* SMBus 0:1f.4 */
+#include "smbus.asl"
+
/* USB XHCI 0:14.0 */
#include "xhci.asl"
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
-
-/* GBe 0:1f.6 */
-#include "pch_glan.asl"
diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl
index 8268bd516f..312cc5a88e 100644
--- a/src/soc/intel/tigerlake/acpi/xhci.asl
+++ b/src/soc/intel/tigerlake/acpi/xhci.asl
@@ -53,19 +53,11 @@ Device (XHCI)
Device (HS08) { Name (_ADR, 8) }
Device (HS09) { Name (_ADR, 9) }
Device (HS10) { Name (_ADR, 10) }
- Device (HS11) { Name (_ADR, 11) }
- Device (HS12) { Name (_ADR, 12) }
-
- /* USBr */
- Device (USR1) { Name (_ADR, 11) }
- Device (USR2) { Name (_ADR, 12) }
/* USB3 */
Device (SS01) { Name (_ADR, 13) }
Device (SS02) { Name (_ADR, 14) }
Device (SS03) { Name (_ADR, 15) }
Device (SS04) { Name (_ADR, 16) }
- Device (SS05) { Name (_ADR, 17) }
- Device (SS06) { Name (_ADR, 18) }
}
}