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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-12-16 23:41:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:01:40 +0000 |
| commit | 2fd49721b17f9020c2b449aad778f011dae7bf46 (patch) | |
| tree | 046e62e13fa9d46542b725bae8e15657ce9e6616 /src/soc/intel/tigerlake/chip.c | |
| parent | 92bd83979f8a7b855a78e9bea2d274d1a4f308b6 (diff) | |
| download | coreboot-2fd49721b17f9020c2b449aad778f011dae7bf46.tar.xz | |
soc/intel/tigerlake: Update chip files
Update chip files to include :
- Update chip.c based on TGL FSP
- Update chip.h based on TGL FSP
- Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
- Update pmc_utils.c and JSL devicetree for build failure
Reference
PCH EDS#576591 vol1 rev1.2
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.c | 69 |
1 files changed, 37 insertions, 32 deletions
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index d05fbdfdde..2637cf8482 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -34,29 +34,51 @@ const char *soc_acpi_name(const struct device *dev) if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0"; + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + } + break; + } + return NULL; + } if (dev->path.type != DEVICE_PATH_PCI) return NULL; switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IGD: return "GFX0"; - case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; - case PCH_DEVFN_USBOTG: return "XDCI"; - case PCH_DEVFN_THERMAL: return "THRM"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_CSE: return "CSE1"; - case PCH_DEVFN_CSE_2: return "CSE2"; - case PCH_DEVFN_CSE_IDER: return "CSED"; - case PCH_DEVFN_CSE_KT: return "CSKT"; - case PCH_DEVFN_CSE_3: return "CSE3"; - case PCH_DEVFN_SATA: return "SATA"; - case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -69,34 +91,17 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; - case PCH_DEVFN_PCIE13: return "RP13"; - case PCH_DEVFN_PCIE14: return "RP14"; - case PCH_DEVFN_PCIE15: return "RP15"; - case PCH_DEVFN_PCIE16: return "RP16"; - case PCH_DEVFN_PCIE17: return "RP17"; - case PCH_DEVFN_PCIE18: return "RP18"; - case PCH_DEVFN_PCIE19: return "RP19"; - case PCH_DEVFN_PCIE20: return "RP20"; - case PCH_DEVFN_PCIE21: return "RP21"; - case PCH_DEVFN_PCIE22: return "RP22"; - case PCH_DEVFN_PCIE23: return "RP23"; - case PCH_DEVFN_PCIE24: return "RP24"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_EMMC: return "EMMC"; - case PCH_DEVFN_SDCARD: return "SDXC"; /* Keeping ACPI device name coherent with ec.asl */ case PCH_DEVFN_ESPI: return "LPCB"; - case PCH_DEVFN_P2SB: return "P2SB"; - case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_GBE: return "IGBE"; - case PCH_DEVFN_TRACEHUB:return "THUB"; + case PCH_DEVFN_GBE: return "GLAN"; } return NULL; @@ -146,9 +151,9 @@ static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, - #if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, - #endif +#endif }; static struct device_operations cpu_bus_ops = { |