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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-01-02 16:11:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 16:03:19 +0000
commit2f2c7ebfb4059220179cd16e2c7d0f422fbe5841 (patch)
treeb632aed51bee1b1725f2a62f88262d9f124d46e6 /src/soc/intel/tigerlake/chip.h
parent6ca5b475bf286ee8827edee64df5d14b09d936cd (diff)
downloadcoreboot-2f2c7ebfb4059220179cd16e2c7d0f422fbe5841.tar.xz
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h24
1 files changed, 11 insertions, 13 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 4f57b0e07a..75a399fc27 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -30,6 +30,10 @@
#include <soc/serialio.h>
#include <soc/usb.h>
+#define MAX_HD_AUDIO_DMIC_LINKS 2
+#define MAX_HD_AUDIO_SNDW_LINKS 4
+#define MAX_HD_AUDIO_SSP_LINKS 6
+
struct soc_intel_tigerlake_config {
/* Common struct containing soc config data required by common code */
@@ -99,20 +103,14 @@ struct soc_intel_tigerlake_config {
uint8_t SataPortsDevSlp[8];
/* Audio related */
- uint8_t PchHdaEnable;
uint8_t PchHdaDspEnable;
-
- /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
- uint8_t PchHdaAudioLinkHda;
- uint8_t PchHdaAudioLinkDmic0;
- uint8_t PchHdaAudioLinkDmic1;
- uint8_t PchHdaAudioLinkSsp0;
- uint8_t PchHdaAudioLinkSsp1;
- uint8_t PchHdaAudioLinkSsp2;
- uint8_t PchHdaAudioLinkSndw1;
- uint8_t PchHdaAudioLinkSndw2;
- uint8_t PchHdaAudioLinkSndw3;
- uint8_t PchHdaAudioLinkSndw4;
+ uint8_t PchHdaAudioLinkHdaEnable;
+ uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
+ uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
+ uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
+ uint8_t PchHdaIDispLinkTmode;
+ uint8_t PchHdaIDispLinkFrequency;
+ uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];