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author | Subrata Banik <subrata.banik@intel.com> | 2020-07-05 19:13:15 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-07-09 12:44:26 +0000 |
commit | 8104effa0dc25bac4693e8d76c1e10039dd47bad (patch) | |
tree | edc8e60e8acc569b90df57145458801ff670d403 /src/soc/intel/tigerlake/chip.h | |
parent | 96dec04207604fdd58ab2f76f8667542c03902e4 (diff) | |
download | coreboot-8104effa0dc25bac4693e8d76c1e10039dd47bad.tar.xz |
mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
Refer to commit 7736bfc
TEST=Able to build and boot TGLRVP.
Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r-- | src/soc/intel/tigerlake/chip.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 26ed64e0f1..fee7105245 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -192,16 +192,6 @@ struct soc_intel_tigerlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * Disable: 0x0 - * 32MB: 0x2000000 - * 64MB: 0x4000000 - * 128 MB: 0x8000000 - * 256 MB: 0x10000000 - * 512 MB: 0x20000000 - */ - uint32_t PrmrrSize; uint8_t PmTimerDisabled; /* * SerialIO device mode selection: |