diff options
author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-01-17 18:56:58 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-27 12:03:42 +0000 |
commit | dba6c4cfc08db8cb41b3f40d9ac9e03f92056046 (patch) | |
tree | 9240c1f9138084d5d49efe3e88764f1d485a738c /src/soc/intel/tigerlake/fsp_params_jsl.c | |
parent | de36d7ebfa52f4cfa2ca9b1f477a2deee6a487f4 (diff) | |
download | coreboot-dba6c4cfc08db8cb41b3f40d9ac9e03f92056046.tar.xz |
soc/intel/tigerlake: Update FSP params for Jasper Lake
Update FSP parameters for various configurations like:
- graphics
- USB
- PCIe root ports
- SD card
- eMMC
- Audio
- Basic UART configuration
These are the initial settings for JSL.
This patch also corrects the debug_interface_flag definitions.
TEST=Build dedede board
Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params_jsl.c')
-rw-r--r-- | src/soc/intel/tigerlake/fsp_params_jsl.c | 143 |
1 files changed, 140 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 6fb2f9f597..8eb3fbacaf 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -12,10 +12,19 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <assert.h> +#include <console/console.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> +#include <fsp/util.h> #include <intelblocks/lpss.h> +#include <intelblocks/mp_init.h> +#include <intelblocks/xdci.h> +#include <soc/intel/common/vbt.h> +#include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <soc/soc_chip.h> +#include <string.h> static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, @@ -32,10 +41,138 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_UART2 }; +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_tigerlake_config *config = config_of_soc(); + + /* LPSS controllers configuration */ + + /* I2C */ + _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= + ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); + memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, + sizeof(config->SerialIoI2cMode)); + + /* GSPI */ + _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= + ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, + sizeof(config->SerialIoGSpiMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= + ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, + sizeof(config->SerialIoGSpiCsMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= + ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, + sizeof(config->SerialIoGSpiCsState)); + + /* UART */ + _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= + ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); + memcpy(params->SerialIoUartMode, config->SerialIoUartMode, + sizeof(config->SerialIoUartMode)); +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - /* TODO: Update with UPD override as FSP matures */ + unsigned int i; + struct device *dev; + FSP_S_CONFIG *params = &supd->FspsConfig; + struct soc_intel_tigerlake_config *config = config_of_soc(); + + /* Parse device tree and fill in FSP UPDs */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + + /* Unlock upper 8 bytes of RTC RAM */ + params->RtcMemoryLock = 0; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + /* USB configuration */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* SDCard related configuration */ + params->ScsSdCardEnabled = pcidev_path_on_root(PCH_DEVFN_SDCARD) ? dev->enabled : 0; + + params->Device4Enable = config->Device4Enable; + + /* eMMC configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + if (!dev) { + params->ScsEmmcEnabled = 0; + } else { + params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + if (!dev || !xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + + /* Provide correct UART number for FSP debug logs */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + + /* Override/Fill FSP Silicon Param for mainboard */ + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Return list of SOC LPSS controllers */ |