diff options
author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2019-12-27 13:28:01 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-22 15:43:12 +0000 |
commit | d801b1feb8a72adaa8d06d8b4d0b63c6e0ff7350 (patch) | |
tree | e277a83bfba77437733bf4a12a61f8fe633c2ab8 /src/soc/intel/tigerlake/fsp_params_tgl.c | |
parent | 9d678f2e56ece95bd9289ad05ec8670d6329ff16 (diff) | |
download | coreboot-d801b1feb8a72adaa8d06d8b4d0b63c6e0ff7350.tar.xz |
soc/intel/tigerlake: Update fsp_params for TGL
Add initial fsp upd settings for TGL, both romstage and ramstage upd's to
support basic build and boot of TGL RVP.
- Add Silicon upd settings which includes
* Serial IO/UART settings
* Graphics settings
* USB2/USB3 settings
- Add Romstage upd settings which includes
* Pcie Root port settings
* IGD initialization
* Hyper Threading settings
* SMBus controller settings
* Debug probe settings
BUG=none
BRANCH=none
TEST=Build and boot Tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params_tgl.c')
-rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 94 |
1 files changed, 93 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 6fb2f9f597..fe59ac1d42 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -13,9 +13,37 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <fsp/api.h> +#include <fsp/util.h> #include <intelblocks/lpss.h> +#include <intelblocks/xdci.h> +#include <soc/gpio_soc_defs.h> +#include <soc/intel/common/vbt.h> +#include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <soc/soc_chip.h> +#include <string.h> + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + const struct soc_intel_tigerlake_config *config; + config = config_of_soc(); + + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; + params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; + } + + for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +} static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, @@ -27,6 +55,7 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_GSPI0, PCH_DEVFN_GSPI1, PCH_DEVFN_GSPI2, + PCH_DEVFN_GSPI3, PCH_DEVFN_UART0, PCH_DEVFN_UART1, PCH_DEVFN_UART2 @@ -35,7 +64,70 @@ static const pci_devfn_t serial_io_dev[] = { /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - /* TODO: Update with UPD override as FSP matures */ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + + struct device *dev; + struct soc_intel_tigerlake_config *config; + config = config_of_soc(); + + /* Parse device tree and enable/disable Serial I/O devices */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + + for (i = 0; i < 8; i++) + params->IomTypeCPortPadCfg[i] = 0x09000000; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + + /* PCH UART selection for FSP Debug */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + + mainboard_silicon_init_params(params); +} + +/* Mainboard GPIO Configuration */ +__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Return list of SOC LPSS controllers */ |