diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-23 10:13:10 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-01 19:12:30 +0000 |
| commit | 555c9b6268febf001e887fbb9e3c3f0901a371ac (patch) | |
| tree | d3b1968356086c05ac0894115f45b06cb8437e85 /src/soc/intel/tigerlake/include/soc/gpio.h | |
| parent | a23e0c9d74b7f06738ebf28b068e1bd63f246982 (diff) | |
| download | coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.tar.xz | |
soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include/soc/gpio.h')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/gpio.h | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h index 7a6df7c74f..1793a3f6fe 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio.h +++ b/src/soc/intel/tigerlake/include/soc/gpio.h @@ -18,21 +18,10 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#if CONFIG(SOC_INTEL_TIGERLAKE) - - #define CROS_GPIO_NAME "INT34C5" - #define CROS_GPIO_COMM0_NAME "INT34C5:00" - #define CROS_GPIO_COMM1_NAME "INT34C5:01" - #define CROS_GPIO_COMM4_NAME "INT34C5:02" - #define CROS_GPIO_COMM5_NAME "INT34C5:03" - -#elif CONFIG(SOC_INTEL_JASPERLAKE) - - #define CROS_GPIO_NAME "INT34C8" - #define CROS_GPIO_COMM0_NAME "INT34C8:00" - #define CROS_GPIO_COMM1_NAME "INT34C8:01" - #define CROS_GPIO_COMM4_NAME "INT34C8:02" - #define CROS_GPIO_COMM5_NAME "INT34C8:03" -#endif +#define CROS_GPIO_NAME "INT34C5" +#define CROS_GPIO_COMM0_NAME "INT34C5:00" +#define CROS_GPIO_COMM1_NAME "INT34C5:01" +#define CROS_GPIO_COMM4_NAME "INT34C5:02" +#define CROS_GPIO_COMM5_NAME "INT34C5:03" #endif |