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authorShaunak Saha <shaunak.saha@intel.com>2020-03-24 00:24:59 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-05-06 15:40:41 +0000
commit56e3df459abafdd9d00fcd0a8ddca7db4730874a (patch)
tree5751617d4fd2db981d697805ab25a196b27290b7 /src/soc/intel/tigerlake/include/soc/gpio.h
parente685107dd61461f91d3fdbf722cf378e121e2551 (diff)
downloadcoreboot-56e3df459abafdd9d00fcd0a8ddca7db4730874a.tar.xz
soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel
Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/include/soc/gpio.h')
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio.h7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index ccf6663865..0ac0033eff 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -7,10 +7,7 @@
#include <soc/gpio_defs.h>
#include <intelblocks/gpio.h>
-#define CROS_GPIO_NAME "INT34C5"
-#define CROS_GPIO_COMM0_NAME "INT34C5:00"
-#define CROS_GPIO_COMM1_NAME "INT34C5:01"
-#define CROS_GPIO_COMM4_NAME "INT34C5:02"
-#define CROS_GPIO_COMM5_NAME "INT34C5:03"
+
+#define CROS_GPIO_DEVICE_NAME "INT34C5:00"
#endif