diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-02-07 22:27:58 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:54:57 +0000 |
| commit | b143e677ee8df130fec1456a47e30f3088139974 (patch) | |
| tree | c78bb5eec507a961adac501f2e66dc951e2d3537 /src/soc/intel/tigerlake/include | |
| parent | cdabc407cde7a7ccea46390b8ed0cfb7b95c826b (diff) | |
| download | coreboot-b143e677ee8df130fec1456a47e30f3088139974.tar.xz | |
src/soc/tigerlake: Accomodate JSP specific changes in iomap.h
Updating MCH, GSPI And I2C base addresses for JSP in iomap header.
BUG=None
BRANCH=None
TEST=Compilation for Jasper lake board is working
Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38754
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/iomap.h | 29 |
1 files changed, 22 insertions, 7 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 2e61477dd4..f403873f10 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -42,12 +42,6 @@ UART_BASE_SIZE * (x))) #define UART_BASE(x) UART_BASE_0_ADDR(x) -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -#define MCH_BASE_ADDRESS 0xfedc0000 -#define MCH_BASE_SIZE 0x20000 - #define DMI_BASE_ADDRESS 0xfeda0000 #define DMI_BASE_SIZE 0x1000 @@ -66,7 +60,6 @@ #define PCH_PWRM_BASE_SIZE 0x10000 #define SPI_BASE_ADDRESS 0xfe010000 -#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 #define GPIO_BASE_SIZE 0x10000 @@ -78,6 +71,28 @@ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) +#if CONFIG(SOC_INTEL_TIGERLAKE) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#else /* CONFIG_SOC_INTEL_JASPERLAKE */ + +#define MCH_BASE_ADDRESS 0xfea80000 +#define MCH_BASE_SIZE 0x8000 + +#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 + +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + +#endif + /* * I/O port address space */ |