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authorMichael Niewöhner <foss@mniewoehner.de>2020-03-03 20:15:02 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-07 20:32:36 +0000
commit7f9ceef51be785781ea4c0035c31d718d590a2fb (patch)
treedcb10c0b61fbb2a75ac542e8cf58d1f7b660fd34 /src/soc/intel/tigerlake/include
parent8034813581ad310d567408f050dfa76d5b29144f (diff)
downloadcoreboot-7f9ceef51be785781ea4c0035c31d718d590a2fb.tar.xz
intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected
Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
-rw-r--r--src/soc/intel/tigerlake/include/soc/pm.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h
index d2f47e271b..588dfba7ba 100644
--- a/src/soc/intel/tigerlake/include/soc/pm.h
+++ b/src/soc/intel/tigerlake/include/soc/pm.h
@@ -132,8 +132,8 @@
* - on writes to GBL_RLS (bios commands)
* - on eSPI events (does nothing on LPC systems)
* No SMIs:
+ * - on TCO events, unless enabled in common code
* - on microcontroller writes (io 0x62/0x66)
- * - on TCO events
*/
#define ENABLE_SMI_PARAMS \
(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS)