diff options
author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-07 23:40:58 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-22 15:42:12 +0000 |
commit | 8406179eff18144cad3584f28554186baf8e1a37 (patch) | |
tree | 8c327435703459c20452dc0255fc988a02ed49b9 /src/soc/intel/tigerlake/include | |
parent | 13471bc86454ec33ca1550706d62386625e7fed1 (diff) | |
download | coreboot-8406179eff18144cad3584f28554186baf8e1a37.tar.xz |
soc/intel/tigerlake: Update interrupt info
Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.
Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
-rw-r--r-- | src/soc/intel/tigerlake/include/soc/irq.h | 130 |
1 files changed, 54 insertions, 76 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 2f980ff472..4d6318f9c5 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,91 +16,69 @@ #ifndef _SOC_IRQ_H_ #define _SOC_IRQ_H_ -#define GPIO_IRQ14 14 -#define GPIO_IRQ15 15 +#define GPIO_IRQ14 14 +#define GPIO_IRQ15 15 -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 -#define SCI_IRQ9 9 -#define SCI_IRQ10 10 -#define SCI_IRQ11 11 -#define SCI_IRQ20 20 -#define SCI_IRQ21 21 -#define SCI_IRQ22 22 -#define SCI_IRQ23 23 +#define LPSS_I2C0_IRQ 27 +#define LPSS_I2C1_IRQ 28 +#define LPSS_I2C2_IRQ 29 +#define LPSS_I2C3_IRQ 30 +#define LPSS_I2C4_IRQ 31 +#define LPSS_I2C5_IRQ 32 +#define LPSS_SPI0_IRQ 36 +#define LPSS_SPI1_IRQ 37 +#define LPSS_SPI2_IRQ 18 +#define LPSS_SPI3_IRQ 23 +#define LPSS_UART0_IRQ 34 +#define LPSS_UART1_IRQ 35 +#define LPSS_UART2_IRQ 33 -#define TCO_IRQ9 9 -#define TCO_IRQ10 10 -#define TCO_IRQ11 11 -#define TCO_IRQ20 20 -#define TCO_IRQ21 21 -#define TCO_IRQ22 22 -#define TCO_IRQ23 23 +#define HDA_IRQ 16 +#define SMBUS_IRQ 16 +#define TRACEHUB_IRQ 16 -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 -#define SDIO_IRQ 22 +#define PCIE_1_IRQ 16 +#define PCIE_2_IRQ 17 +#define PCIE_3_IRQ 18 +#define PCIE_4_IRQ 19 +#define PCIE_5_IRQ 16 +#define PCIE_6_IRQ 17 +#define PCIE_7_IRQ 18 +#define PCIE_8_IRQ 19 +#define PCIE_9_IRQ 16 +#define PCIE_10_IRQ 17 +#define PCIE_11_IRQ 18 +#define PCIE_12_IRQ 19 -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 +#define SATA_IRQ 16 -#define eMMC_IRQ 16 -#define SD_IRQ 19 +#define xHCI_IRQ 16 +#define xDCI_IRQ 17 +#define CNVI_WIFI_IRQ 16 -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 +#define CNVI_BT_IRQ 18 -#define SATA_IRQ 16 +#define THC0_IRQ 16 +#define THC1_IRQ 17 -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define IDER_IRQ 18 -#define KT_IRQ 19 -#define HECI_3_IRQ 16 +#define ISH_IRQ 16 -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define PMC_SRAM_IRQ 18 -#define THERMAL_IRQ 16 -#define CNViWIFI_IRQ 19 -#define UFS_IRQ 16 -#define CIO_INTA_IRQ 16 -#define CIO_INTD_IRQ 19 -#define ISH_IRQ 20 +#define TBT_PCIe0_IRQ 16 +#define TBT_PCIe1_IRQ 17 +#define TBT_PCIe2_IRQ 18 +#define TBT_PCIe3_IRQ 19 -#define PEG_RP_INTA_IRQ 16 -#define PEG_RP_INTB_IRQ 17 -#define PEG_RP_INTC_IRQ 18 -#define PEG_RP_INTD_IRQ 19 +#define HECI_1_IRQ 16 +#define HECI_2_IRQ 17 +#define HECI_3_IRQ 16 +#define HECI_4_IRQ 19 -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 +#define PEG_IRQ 16 +#define IGFX_IRQ 16 +#define THERMAL_IRQ 16 +#define IPU_IRQ 16 +#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ |