diff options
author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-12-16 23:28:36 -0800 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-15 14:30:07 +0000 |
commit | fbd6869f918803852352878b0c6138f080780503 (patch) | |
tree | 3a8bcbbce61dd78e6f70d8b57145b3a44627af88 /src/soc/intel/tigerlake/include | |
parent | 607ee30403629c4a8542be2686bd27dc508b3987 (diff) | |
download | coreboot-fbd6869f918803852352878b0c6138f080780503.tar.xz |
soc/intel/tigerlake: Update header files
Modify header files to update/include tigerlake:
- IOMAP BARs according to silicon reference code
- Update Serial IO devices according to PCH EDS
- Add board types
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
-rw-r--r-- | src/soc/intel/tigerlake/include/soc/iomap.h | 22 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/include/soc/romstage.h | 8 | ||||
-rw-r--r-- | src/soc/intel/tigerlake/include/soc/serialio.h | 9 |
3 files changed, 28 insertions, 11 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 72ac25fdc3..2e61477dd4 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -34,11 +34,19 @@ #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 -#define EARLY_I2C_BASE_ADDRESS 0xfe040000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) +#define UART_BASE_SIZE 0x1000 -#define MCH_BASE_ADDRESS 0xfed10000 -#define MCH_BASE_SIZE 0x8000 +#define UART_BASE_0_ADDRESS 0xfe03e000 +/* Both UART BAR 0 and 1 are 4KB in size */ +#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \ + UART_BASE_SIZE * (x))) +#define UART_BASE(x) UART_BASE_0_ADDR(x) + +#define EARLY_I2C_BASE_ADDRESS 0xfe020000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) + +#define MCH_BASE_ADDRESS 0xfedc0000 +#define MCH_BASE_SIZE 0x20000 #define DMI_BASE_ADDRESS 0xfeda0000 #define DMI_BASE_SIZE 0x1000 @@ -49,7 +57,7 @@ #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 -#define REG_BASE_ADDRESS 0xfc000000 +#define REG_BASE_ADDRESS 0xfb000000 #define REG_BASE_SIZE 0x1000 #define HPET_BASE_ADDRESS 0xfed00000 @@ -58,13 +66,13 @@ #define PCH_PWRM_BASE_SIZE 0x10000 #define SPI_BASE_ADDRESS 0xfe010000 -#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 +#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 #define GPIO_BASE_SIZE 0x10000 #define HECI1_BASE_ADDRESS 0xfeda2000 -#define VTD_BASE_ADDRESS 0xFED90000 +#define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index 046e856920..98ed6bc158 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -22,4 +22,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); void pch_init(void); +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; + #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/serialio.h b/src/soc/intel/tigerlake/include/soc/serialio.h index cdf55157ff..04c0efe19b 100644 --- a/src/soc/intel/tigerlake/include/soc/serialio.h +++ b/src/soc/intel/tigerlake/include/soc/serialio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,19 +30,20 @@ enum { PchSerialIoIndexI2C2, PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5 + PchSerialIoIndexI2C5, }; enum { PchSerialIoIndexGSPI0, PchSerialIoIndexGSPI1, - PchSerialIoIndexGSPI2 + PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI3, }; enum { PchSerialIoIndexUART0, PchSerialIoIndexUART1, - PchSerialIoIndexUART2 + PchSerialIoIndexUART2, }; #endif |