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| author | John Su <john_su@compal.corp-partner.google.com> | 2020-01-31 14:02:40 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 15:55:43 +0000 |
| commit | 3e89b65c2cf634c1ba81da65d42aa64b53c5b244 (patch) | |
| tree | 7f7c43ba93e315e46488a6d9764129bb27ebd82d /src/soc/intel/tigerlake/include | |
| parent | 75909184fefac9ade704f9cfe4bc220803ed39f3 (diff) | |
| download | coreboot-3e89b65c2cf634c1ba81da65d42aa64b53c5b244.tar.xz | |
mb/google/drallion/variants/drallion: Update thermal configuration for DPTF
Follow thermal table for fine tuning.
1. Update PSV values for sensors.
2. Change PL1 min value from 4W to 5W.
3. Change PL1 max value from 15W to 12W.
4. Change PL2 min value from 15W to 12W.
BUG=b:148627484
TEST=Built and tested on drallion
Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
0 files changed, 0 insertions, 0 deletions