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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-01-17 18:56:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-27 12:03:42 +0000 |
| commit | dba6c4cfc08db8cb41b3f40d9ac9e03f92056046 (patch) | |
| tree | 9240c1f9138084d5d49efe3e88764f1d485a738c /src/soc/intel/tigerlake/include | |
| parent | de36d7ebfa52f4cfa2ca9b1f477a2deee6a487f4 (diff) | |
| download | coreboot-dba6c4cfc08db8cb41b3f40d9ac9e03f92056046.tar.xz | |
soc/intel/tigerlake: Update FSP params for Jasper Lake
Update FSP parameters for various configurations like:
- graphics
- USB
- PCIe root ports
- SD card
- eMMC
- Audio
- Basic UART configuration
These are the initial settings for JSL.
This patch also corrects the debug_interface_flag definitions.
TEST=Build dedede board
Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 9a35e73252..ef2dfe3ec4 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -86,6 +86,11 @@ #define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) +#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) +#endif + #define PCH_DEV_SLOT_SIO3 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) @@ -122,6 +127,12 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define PCH_DEV_SLOT_STORAGE 0x1a +#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#endif + #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) |