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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-04-02 19:19:06 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-11 21:31:54 +0000
commit9a90a439a2f142ea22ad66584e93b1f309e00dd9 (patch)
tree2eda83a4599f4090e2cf00e560b4364497e198ce /src/soc/intel/tigerlake/meminit.c
parent083379d0f8a8524c4ffc708350c3e2c9fae683af (diff)
downloadcoreboot-9a90a439a2f142ea22ad66584e93b1f309e00dd9.tar.xz
soc/intel/tigerlake: Disable MrcSafeConfig
This change disables MrcSafeConfig option during MRC training. MrcSafeConfig was enabled as part of the early testing. Now with FSP 2527, there is no need to set this config anymore. BUG=b:150357377 BRANCH=master TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/meminit.c')
-rw-r--r--src/soc/intel/tigerlake/meminit.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c
index 7823cfe523..86645472aa 100644
--- a/src/soc/intel/tigerlake/meminit.c
+++ b/src/soc/intel/tigerlake/meminit.c
@@ -239,7 +239,6 @@ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg,
/* LPDDR4x does not allow interleaved memory */
mem_cfg->DqPinsInterleaved = 0;
mem_cfg->ECT = board_cfg->ect;
- mem_cfg->MrcSafeConfig = 0x1;
read_md_spd(info, &spd_data, &spd_len);
mem_cfg->MemorySpdDataLen = spd_len;