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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-04-02 15:31:21 -0700
committerFurquan Shaikh <furquan@google.com>2020-04-05 19:10:05 +0000
commita5c27096a41a715efda103b03bf3ce2a61ff1670 (patch)
tree93dd364d4665b47c6fa7bf59749efb87c994c151 /src/soc/intel/tigerlake/meminit.c
parente67ab180fb856b25f3fbb238438606446a7e3ddb (diff)
downloadcoreboot-a5c27096a41a715efda103b03bf3ce2a61ff1670.tar.xz
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD. BUG=b:152000235 BRANCH=none TEST= build volteer and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40061 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/meminit.c')
-rw-r--r--src/soc/intel/tigerlake/meminit.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c
index 864f0795e4..bd9a4ff45d 100644
--- a/src/soc/intel/tigerlake/meminit.c
+++ b/src/soc/intel/tigerlake/meminit.c
@@ -40,45 +40,53 @@ static uint8_t get_dimm_cfg(uintptr_t dimm0, uintptr_t dimm1)
static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0,
uintptr_t spd_dimm1)
{
- mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1);
+ uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1);
switch (channel) {
case 0:
+ mem_cfg->DisableDimmCh0 = dimm_cfg;
mem_cfg->MemorySpdPtr00 = spd_dimm0;
mem_cfg->MemorySpdPtr01 = spd_dimm1;
break;
case 1:
+ mem_cfg->DisableDimmCh1 = dimm_cfg;
mem_cfg->MemorySpdPtr02 = spd_dimm0;
mem_cfg->MemorySpdPtr03 = spd_dimm1;
break;
case 2:
+ mem_cfg->DisableDimmCh2 = dimm_cfg;
mem_cfg->MemorySpdPtr04 = spd_dimm0;
mem_cfg->MemorySpdPtr05 = spd_dimm1;
break;
case 3:
+ mem_cfg->DisableDimmCh3 = dimm_cfg;
mem_cfg->MemorySpdPtr06 = spd_dimm0;
mem_cfg->MemorySpdPtr07 = spd_dimm1;
break;
case 4:
+ mem_cfg->DisableDimmCh4 = dimm_cfg;
mem_cfg->MemorySpdPtr08 = spd_dimm0;
mem_cfg->MemorySpdPtr09 = spd_dimm1;
break;
case 5:
+ mem_cfg->DisableDimmCh5 = dimm_cfg;
mem_cfg->MemorySpdPtr10 = spd_dimm0;
mem_cfg->MemorySpdPtr11 = spd_dimm1;
break;
case 6:
+ mem_cfg->DisableDimmCh6 = dimm_cfg;
mem_cfg->MemorySpdPtr12 = spd_dimm0;
mem_cfg->MemorySpdPtr13 = spd_dimm1;
break;
case 7:
+ mem_cfg->DisableDimmCh7 = dimm_cfg;
mem_cfg->MemorySpdPtr14 = spd_dimm0;
mem_cfg->MemorySpdPtr15 = spd_dimm1;
break;