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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-12-16 23:41:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-18 11:01:40 +0000 |
| commit | 2fd49721b17f9020c2b449aad778f011dae7bf46 (patch) | |
| tree | 046e62e13fa9d46542b725bae8e15657ce9e6616 /src/soc/intel/tigerlake/pmutil.c | |
| parent | 92bd83979f8a7b855a78e9bea2d274d1a4f308b6 (diff) | |
| download | coreboot-2fd49721b17f9020c2b449aad778f011dae7bf46.tar.xz | |
soc/intel/tigerlake: Update chip files
Update chip files to include :
- Update chip.c based on TGL FSP
- Update chip.h based on TGL FSP
- Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
- Update pmc_utils.c and JSL devicetree for build failure
Reference
PCH EDS#576591 vol1 rev1.2
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/pmutil.c')
| -rw-r--r-- | src/soc/intel/tigerlake/pmutil.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 39734bb4e9..84a93aebbc 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -189,9 +189,9 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) config = config_of_soc(); /* Assign to out variable */ - *dw0 = config->gpe0_dw0; - *dw1 = config->gpe0_dw1; - *dw2 = config->gpe0_dw2; + *dw0 = config->pmc_gpe0_dw0; + *dw1 = config->pmc_gpe0_dw1; + *dw2 = config->pmc_gpe0_dw2; } static int rtc_failed(uint32_t gen_pmcon_b) |