diff options
author | Felix Singer <felixsinger@posteo.net> | 2020-07-26 09:22:42 +0200 |
---|---|---|
committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-28 08:36:59 +0000 |
commit | 5c10704f58982d62a1326e5d6ff9956e0eaf6e16 (patch) | |
tree | 0ec8560aba88de53168b21a71c4b74c9b314216c /src/soc/intel/tigerlake/romstage | |
parent | 0f823095620e9b6434e9c731468526654a7725ae (diff) | |
download | coreboot-5c10704f58982d62a1326e5d6ff9956e0eaf6e16.tar.xz |
soc/intel/tigerlake: Simplify is-device-enabled checks
Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: I791273e5dd633cd1d6218b322106e2f62a393259
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage')
-rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 60 |
1 files changed, 18 insertions, 42 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index b12faecd24..acb366bb4a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -3,6 +3,7 @@ #include <assert.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <device/device.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> @@ -21,16 +22,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, uint32_t cpu_id, mask = 0; const struct device *dev; + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (!dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled in devicetree.cb */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - } + m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -76,7 +74,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - if (dev && dev->enabled && config->TraceHubMode) { + if (is_dev_enabled(dev) && config->TraceHubMode) { m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; m_cfg->PchTraceHubMode = config->TraceHubMode; m_cfg->CpuTraceHubMode = config->TraceHubMode; @@ -87,10 +85,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (!dev || !dev->enabled) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = 1; + m_cfg->PchIshEnable = is_dev_enabled(dev); /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; @@ -119,39 +114,23 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* TCSS DMA */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - if (dev) - m_cfg->TcssDma0En = dev->enabled; - else - m_cfg->TcssDma0En = 0; + m_cfg->TcssDma0En = is_dev_enabled(dev); dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); - if (dev) - m_cfg->TcssDma1En = dev->enabled; - else - m_cfg->TcssDma1En = 0; + m_cfg->TcssDma1En = is_dev_enabled(dev); /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); - if (dev) - m_cfg->TcssItbtPcie0En = dev->enabled; - else - m_cfg->TcssItbtPcie0En = 0; + m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + dev = pcidev_path_on_root(SA_DEVFN_TBT1); - if (dev) - m_cfg->TcssItbtPcie1En = dev->enabled; - else - m_cfg->TcssItbtPcie1En = 0; + m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); dev = pcidev_path_on_root(SA_DEVFN_TBT2); - if (dev) - m_cfg->TcssItbtPcie2En = dev->enabled; - else - m_cfg->TcssItbtPcie2En = 0; + m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); + dev = pcidev_path_on_root(SA_DEVFN_TBT3); - if (dev) - m_cfg->TcssItbtPcie3En = dev->enabled; - else - m_cfg->TcssItbtPcie3En = 0; + m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); /* Hyper Threading */ m_cfg->HyperThreading = !config->HyperThreadingDisable; @@ -167,10 +146,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaEnable = is_dev_enabled(dev); m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; |