diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2020-04-06 15:31:34 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:13:16 +0000 |
| commit | 71d365d4583064da85e3f6544e2fbd385cf1e8b3 (patch) | |
| tree | 6d28d4269c79b1550226f23e5deb60a89eb1171f /src/soc/intel/tigerlake | |
| parent | b9907042d424ba6b974574240c20a40fb23b3509 (diff) | |
| download | coreboot-71d365d4583064da85e3f6544e2fbd385cf1e8b3.tar.xz | |
soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg
In order for the SOC to be able to control the Aux line orientation for
Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs
to be configurable through devicetree to correctly set the GPIO pins that
the SOC should use to flip orientation.
BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped
Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 2 |
2 files changed, 14 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3047037183..a32cebe594 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -222,6 +222,19 @@ struct soc_intel_tigerlake_config { uint8_t TcssDma1En; /* + * IOM Port Config + * If a port orientation needs to be controlled by the SOC this setting must be + * updated to reflect the correct GPIOs being used for the SOC port flipping. + * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down + * 0,1 are pull up and pull down for port 0 + * 2,3 are pull up and pull down for port 1 + * 4,5 are pull up and pull down for port 2 + * 6,7 are pull up and pull down for port 3 + * values to be programmed correspond to the GPIO family and offsets + */ + uint32_t IomTypeCPortPadCfg[8]; + + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 73c41c8519..cf106cbe16 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -103,7 +103,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = 0x09000000; + params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |