diff options
| author | John Zhao <john.zhao@intel.com> | 2020-07-27 13:22:11 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-07-29 22:46:29 +0000 |
| commit | bd615d6f9379cc454c728c8f79f13612f3fb7a19 (patch) | |
| tree | 57bd7c98bc93aaf70576f75d336b4026098c870c /src/soc/intel/tigerlake | |
| parent | 048d9b5cba64d1dbffc40ee19a5263aeac628e3c (diff) | |
| download | coreboot-bd615d6f9379cc454c728c8f79f13612f3fb7a19.tar.xz | |
soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
Update configuration for both of TCSS D3Hot and D3Cold. It is expected
D3Hot is enabled for all platforms. Because there are known limitations
for D3Cold enabling on pre-QS platform, this change reads cpu id and
disables D3Cold for pre-QS platform. For QS platform, D3Cold is
configured to be enabled.
BUG=None
TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0)
and enabled for QS (cpu:0x806c1).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 10 |
2 files changed, 10 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 812dbacb1c..dc910ff4c0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -79,9 +79,9 @@ struct soc_intel_tigerlake_config { /* Enable S0iX support */ int s0ix_enable; /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ - uint8_t TcssD3HotEnable; + uint8_t TcssD3HotDisable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t TcssD3ColdEnable; + uint8_t TcssD3ColdDisable; /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 79ce04b5a7..517d771705 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/lpss.h> +#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <security/vboot/vboot_common.h> @@ -85,6 +86,7 @@ static const pci_devfn_t serial_io_dev[] = { void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; + uint32_t cpu_id; FSP_S_CONFIG *params = &supd->FspsConfig; struct device *dev; @@ -110,8 +112,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* D3Hot and D3Cold for TCSS */ - params->D3HotEnable = config->TcssD3HotEnable; - params->D3ColdEnable = config->TcssD3ColdEnable; + params->D3HotEnable = !config->TcssD3HotDisable; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) + params->D3ColdEnable = 0; + else + params->D3ColdEnable = !config->TcssD3ColdDisable; params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++) |