diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 19:45:35 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-05 03:59:08 +0000 |
| commit | d2becae223105b8907e38627bb737d6a521f4c39 (patch) | |
| tree | deb7c8328dc98e8f7c7e1d5ea9f54a3234712595 /src/soc/intel/tigerlake | |
| parent | 34cf7ccebc858b7543856fb0d736ff7809ae9e6c (diff) | |
| download | coreboot-d2becae223105b8907e38627bb737d6a521f4c39.tar.xz | |
soc/intel/common/block/acpi: Factor out common pch_glan.asl
This patch moves pch_glan.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.
TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify GLAN device present inside
common pch_glan.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/pch_glan.asl | 14 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/southbridge.asl | 3 |
2 files changed, 3 insertions, 14 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl deleted file mode 100644 index 97faf7ac80..0000000000 --- a/src/soc/intel/tigerlake/acpi/pch_glan.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel Gigabit Ethernet Controller 0:1f.6 */ - -Device (GLAN) -{ - Name (_ADR, 0x001f0006) - - Name (_S0W, 3) - - Name (_PRW, Package() {GPE0_PME_B0, 4}) - - Method (_DSW, 3) {} -} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index ff683cf4f6..b193de49c3 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -43,3 +43,6 @@ /* PMC Core*/ #include <soc/intel/common/block/acpi/acpi/pmc.asl> + +/* GbE 0:1f.6 */ +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> |