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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-31 00:13:55 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-02 16:45:22 +0000 |
| commit | e2f5fb254989398e7b8ed3e203928825ace4417c (patch) | |
| tree | 35ba407b4e0eb63ca88c62cea1099ef276410053 /src/soc/intel/tigerlake | |
| parent | 13cd145e02e1a197b4ea01095916bf4bb5f77722 (diff) | |
| download | coreboot-e2f5fb254989398e7b8ed3e203928825ace4417c.tar.xz | |
vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms.
Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions