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authorderek.huang <derek.huang@intel.corp-partner.google.com>2020-05-04 18:09:36 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-06-03 01:30:25 +0000
commitbebb2a1705b697fccf91a0f2c3a9d5870a27e9fa (patch)
tree8e036c5760647cd920123cfe2a16aecc83605416 /src/soc/intel/tigerlake
parent5f86b0b7e3153240cfee3dbaade0428c8055ba5b (diff)
downloadcoreboot-bebb2a1705b697fccf91a0f2c3a9d5870a27e9fa.tar.xz
soc/intel/tigerlake: update elog to include CSME reset causes
Call out the CSME-initiated bits from HPR_CAUSE0 register and update the elog to include reset causes Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/elog.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 586dbfdd24..d5b875419a 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -61,6 +61,18 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
elog_add_event(ELOG_TYPE_THERM_TRIP);
+ /* CSME-Initiated Host Reset with power down */
+ if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPD)
+ elog_add_event(ELOG_TYPE_MI_HRPD);
+
+ /* CSME-Initiated Host Reset with power cycle */
+ if (ps->hpr_cause0 & HPR_CAUSE0_MI_HRPC)
+ elog_add_event(ELOG_TYPE_MI_HRPC);
+
+ /* CSME-Initiated Host Reset without power cycle */
+ if (ps->hpr_cause0 & HPR_CAUSE0_MI_HR)
+ elog_add_event(ELOG_TYPE_MI_HR);
+
/* PWR_FLR Power Failure */
if (ps->gen_pmcon_a & PWR_FLR)
elog_add_event(ELOG_TYPE_POWER_FAIL);