diff options
| author | derek.huang <derek.huang@intel.corp-partner.google.com> | 2020-04-23 14:55:24 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-06 08:48:24 +0000 |
| commit | e685107dd61461f91d3fdbf722cf378e121e2551 (patch) | |
| tree | 6dca5dff27e49b7ef52f1b3f296610fbd13ad492 /src/soc/intel/tigerlake | |
| parent | 18e632f8b33b8c764db124e65b9ccab16044f108 (diff) | |
| download | coreboot-e685107dd61461f91d3fdbf722cf378e121e2551.tar.xz | |
soc/intel/tigerlake: Print HPR_CAUSE0 register
In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value
of HPR_CAUSE0.
Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pm.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pmutil.c | 3 |
3 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index c42e280ed1..c69fe3edb8 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -150,6 +150,7 @@ struct chipset_power_state { uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; uint32_t gblrst_cause[2]; + uint32_t hpr_cause0; uint32_t prev_sleep_state; } __packed; diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index 88c6f61d94..9ad3391348 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -119,6 +119,10 @@ #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define HPR_CAUSE0 0x192C +#define HPR_CAUSE0_MI_HRPD (1 << 10) +#define HPR_CAUSE0_MI_HRPC (1 << 9) +#define HPR_CAUSE0_MI_HR (1 << 8) #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 4482b1ec55..554932bd72 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -260,12 +260,15 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + ps->hpr_cause0 = read32(pmc + HPR_CAUSE0); printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b); printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); + + printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } /* STM Support */ |