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authorSubrata Banik <subrata.banik@intel.com>2020-02-27 19:39:22 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-03-01 07:21:41 +0000
commit56626cf5d88523ed274c27e9624de7a358efe835 (patch)
tree258496fee72564d6cc2f525ffa29a1b0948cf247 /src/soc/intel/tigerlake
parent3db439eb1ade91a28cdb34d58b7908024b12d406 (diff)
downloadcoreboot-56626cf5d88523ed274c27e9624de7a358efe835.tar.xz
soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/Kconfig15
-rw-r--r--src/soc/intel/tigerlake/chip.h11
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_jsl.c2
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c2
4 files changed, 17 insertions, 13 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 79d74b4083..8d066f3d45 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -212,4 +212,19 @@ config FSP_FD_PATH
default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE
default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE
+config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
+ int "Debug Consent for TGL"
+ # USB DBC is more common for developers so make this default to 3 if
+ # SOC_INTEL_DEBUG_CONSENT=y
+ default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 0
+ help
+ This is to control debug interface on SOC.
+ Setting non-zero value will allow to use DBC or DCI to debug SOC.
+ PlatformDebugConsent in FspmUpd.h has the details.
+
+ Desired platform debug type are
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+ 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+ 6:Enable (2-wire DCI OOB), 7:Manual
endif
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 54423613dc..02855b1b00 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -169,17 +169,6 @@ struct soc_intel_tigerlake_config {
*/
uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
- /* Desired platform debug type. */
- enum {
- DebugConsent_Disabled,
- DebugConsent_DCI_DBC,
- DebugConsent_DCI,
- DebugConsent_USB3_DBC,
- DebugConsent_XDP, /* XDP/Mipi60 */
- DebugConsent_USB2_DBC,
- DebugConsent_2WIRE_DCI,
- DebugConsent_Manual,
- } DebugConsent;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
index 829e1e35ea..56124f4c04 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
@@ -80,7 +80,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = config->DebugConsent;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* VT-d config */
m_cfg->VtdDisable = 0;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index ed6aa5a221..d76961515f 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -109,7 +109,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Enable SMBus controller based on config */
m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = config->DebugConsent;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;