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| author | Rob Barnes <robbarnes@google.com> | 2020-02-20 14:35:51 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-03-19 10:31:08 +0000 |
| commit | 5baadba532aec78d76d2ba1efea825b5f9b75efc (patch) | |
| tree | 160a556a186f5c49923f86152ec4800de617fd66 /src/soc/intel/tigerlake | |
| parent | 9d49598cd6f323d0119d905f9917f526e0c2920f (diff) | |
| download | coreboot-5baadba532aec78d76d2ba1efea825b5f9b75efc.tar.xz | |
util/bincfg: Add DDR4 SPD spec
Additionally provide a simple script for decoding spd hex files using bincfg.
BUG=b:148561711
TEST=Decoded spd files in zork
BRANCH=None
Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/2067697
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions