summaryrefslogtreecommitdiff
path: root/src/soc/intel/tigerlake
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2020-07-30 11:31:55 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-08-01 06:55:36 +0000
commit6362de3829c1762632e3aa16b1af0fd0a9a1e625 (patch)
tree02298fb9fa0c11fc74dc67743a2cdbeaf38d07c5 /src/soc/intel/tigerlake
parent46f807324916f223282e5c8fee1bfe4595eeb1f2 (diff)
downloadcoreboot-6362de3829c1762632e3aa16b1af0fd0a9a1e625.tar.xz
soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU feature programming on all cores (BSP + APs). Setting SkipMpInit=1 is not recommended as it will only limit CPU feature programming on BSP. TEST=Able to perform CPU feature programming by FSP on all cores using external MP PPI services. Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 517d771705..a61a0255bc 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -104,12 +104,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
/* Use coreboot MP PPI services if Kconfig is enabled */
- if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
- params->SkipMpInit = 0;
- } else {
- params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
- }
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable;