diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-23 15:45:00 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-15 17:49:39 +0000 |
| commit | c2503dbe8864a3a3b917f08794d2414455118891 (patch) | |
| tree | 2762cb175d4e93bfa46fe907418e9e0d5ec150f9 /src/soc/intel/tigerlake | |
| parent | 6452a9fcfc072f85101abf0f476e10c6727d6b69 (diff) | |
| download | coreboot-c2503dbe8864a3a3b917f08794d2414455118891.tar.xz | |
soc/intel/xeon_sp: Fix final MTRR usage
The region top_of_ram -> cbmem_top is used by FSP and cbmem, but is
also just regular DRAM. Marking it as such improves the final MTRR
solution a lot and fixes MTRR starvation depending on the setup.
Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47868
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions