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authorJohn Zhao <john.zhao@intel.com>2020-03-10 11:03:02 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 12:52:26 +0000
commitee47fe42f57b47c5fa301966bbb709abc775f66c (patch)
tree3562cb15e6425570b491c86a0c302267bbbf0ff1 /src/soc/intel/tigerlake
parent6e5693386ba94ebf05015e7cbcc7dd482119c8e4 (diff)
downloadcoreboot-ee47fe42f57b47c5fa301966bbb709abc775f66c.tar.xz
soc/intel/tigerlake: Configure Vmx support using Kconfig
Change VmxEnable UPD value based on Kconfig ENABLE_VMX BUG=None TEST=Built image and booted to kernel. Change-Id: I725474643193223865a135813cf882fd7636d24a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 072c99ea7e..3872b61cf7 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -145,6 +145,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS;
m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS;
m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS;
+
+ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)