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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-05-13 11:42:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:00:27 +0000 |
| commit | c4b70276ed525bfcc59320b72bcd7c8cd13b78f0 (patch) | |
| tree | 2258b8340dc702bb33adbae752575a29f8b8a7f6 /src/soc/intel/tigerlake | |
| parent | 189e753cbfc3b3b2c7cca70215610fb3da6267be (diff) | |
| download | coreboot-c4b70276ed525bfcc59320b72bcd7c8cd13b78f0.tar.xz | |
src: Remove leading blank lines from SPDX header
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/Makefile.inc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 2de1a57467..a1a6c6638d 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -1,6 +1,3 @@ -# -# -# # SPDX-License-Identifier: GPL-2.0-only romstage-y += fsp_params.c |