diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2020-07-08 23:11:01 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-25 04:46:44 +0000 |
| commit | e4109ff54ff3268fe65739e8efe79b57e67d2e3c (patch) | |
| tree | e65322e001ba95ec4c45473276ba18455e886f96 /src/soc/intel/tigerlake | |
| parent | 7cd8c79177ecf2143e878a8e2be916bfe222a8c7 (diff) | |
| download | coreboot-e4109ff54ff3268fe65739e8efe79b57e67d2e3c.tar.xz | |
soc/intel/tigerlake: Update Pkg C-State latencies
Update to recommended C-state entry/exit latencies as per
BWG(611569) Rev 0.8: section 4.5.3.2.2
BUG=none
TEST=Boot to OS and check C-State latencies
"cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/cpu.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 28dfb386c9..47a41ebc99 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -7,11 +7,11 @@ /* Latency times in us */ #define C1_LATENCY 1 -#define C6_LATENCY 127 -#define C7_LATENCY 253 -#define C8_LATENCY 260 -#define C9_LATENCY 487 -#define C10_LATENCY 1048 +#define C6_LATENCY 121 +#define C7_LATENCY 152 +#define C8_LATENCY 256 +#define C9_LATENCY 340 +#define C10_LATENCY 1034 /* Power in units of mW */ #define C1_POWER 0x3e8 |