soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 6 insertions, 36 deletions

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 59350bf967..e05fea2448 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -13,46 +13,16 @@
 ## GNU General Public License for more details.
 ##
 
-ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y)
+ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
 
-subdirs-y += ../../../cpu/intel/microcode
-subdirs-y += ../../../cpu/intel/turbo
-subdirs-y += ../../../cpu/x86/lapic
-subdirs-y += ../../../cpu/x86/mtrr
-subdirs-y += ../../../cpu/x86/tsc
-subdirs-y += ../../../cpu/x86/cache
-subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
+subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
 
-bootblock-y += bootblock/bootblock.c
-bootblock-y += lpc.c
-bootblock-y += spi.c
-
-postcar-y += soc_util.c
+bootblock-y += bootblock.c spi.c lpc.c
+romstage-y += romstage.c reset.c util.c spi.c
+ramstage-y += uncore.c reset.c util.c lpc.c spi.c
 postcar-y += spi.c
 
-romstage-y += soc_util.c
-romstage-y += reset.c
-romstage-y += romstage.c
-romstage-y += soc_util.c
-romstage-y += spi.c
-romstage-y += hob_display.c
-romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
-romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-
-ramstage-y += soc_util.c
-ramstage-y += uncore.c
-ramstage-y += reset.c
-ramstage-y += chip.c
-ramstage-y += soc_util.c
-ramstage-y += lpc.c
-ramstage-y += cpu.c
-ramstage-y += spi.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
-ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += hob_display.c
-
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
 CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
 
-endif ## CONFIG_SOC_INTEL_XEON_SP
+endif ## XEON_SP_COMMON_BASE